1. Field of the Invention
This invention relates to an integrated circuit having insulated gate field effect transistors (IGFET) which is well known in general as a MOS-IC.
2. Description of the Prior Art
In an integrated circuit which comprises an IGFET as the principal element, improvement in the operating speed and integration density is greatly requested. In order to improve such operation speed, it is an effective means to reduce the parasitic junction capacitance incorporated in to the source or drain regions of the IGFET, and the reduction of this parasitic junction capacitance is attained by reducing an area of the pn junction formed around the source or drain region, or by setting the impurity concentration at the area near the pn junction to lower levels. Elimination of an area having high impurity concentration near to this pn junction is desired also for avoiding reduction of the break down voltage at the junction area. On the other hand, for the improvement of integration density, it is necessary not only to make each IGFET small in size but also to reduce the area occupied by the wiring pattern by increasing the degree of freedom of the wirings.
As the means for reducing junction capacitance, the so-called SOS configuration is well known, wherein a silicon layer for the active layer is formed by epitaxial growth on a sapphire substrate. However, the SOS type device basically has such inevitable disadvantages as deterioration of the crystalline characteristic of the active layer related to the hetero-epitaxial configuration and the high cost of the sapphire substrate. A device having no such disadvantages and reduced junction capacitance is indicated in "A New Isolation Structure for High Density LSI", by S. Iwamatsu et al., IEDM Technical Digest, 1973, page 244-247. A device indicated in this material has comparatively high impurity concentration as shown in FIG. 1, wherein the cross section is indicated. This device characteristically comprises the semiconductor substrate 1, the buried insulating film 2 which is formed on the substrate and has an aperture, the epitaxial layer 3 which is formed at the aperture with low impurity concentration and the silicon layer 4 which is formed through growth together with the epitaxial layer 3 and shows a polycrystal characteristic on the insulating film 2. The IGFET is composed of the gate electrode 5 formed on the epitaxial layer 3, the insulating film 6, the metallic layer 7 for electrodes or wiring and the source or drain region 8 which is formed within the epitaxial layer 3 with a high impurity concentration of the opposite conductivity type. This IGFET has the advantage that the area of the pn junction formed along the circumference of the source and drain region 8 is significantly smaller than that of the prior art IG FETS. This reduces the abovementioned parasitic capacitance. On the other hand, in the integrated circuit having plural IG FETs, the wirings are established by conductive layers on the wiring layers as in the case of existing ICs and therefore it is requested to improve the degree of freedom of the wirings.
As taught in the abovementioned reference, the device shown in FIG. 2 adapts the IG FET shown in FIG. 1 to the complementary type integrated circuits. In FIG. 2, the IG FET 10 of the n channel type has the same structure as that of FIG. 1 and the same portions of FIG. 1 are given the same numbering. The substrate 11 has comparatively high N type impurity concentration and is covered with the p channel type IG FET 20 having the p type regions 18 for the source of and drain and gate electrode 15. The n channel type IG FET 10 is formed on the p type region (p type well) 12 having a comparatively high impurity concentration. Since the p type well 12 is formed by introducing the p type impurity through the aperture of the buried insulating film 2, it can be provided independently for an aperture of a n channel IG FET. Thus, the p type epitaxial layer 3 and p type well 12 are electrically floating and they are so small in size that when a small amount of charge is injected therein the potential is easily changed thereby. When the potential of the epitaxial layer 3 and p type well 12 changes, the gate threshold voltage of the IG FET 10 provided thereon also changes due to the well known back gate effect, often resulting defective-operation. Moreover, since an electrode which is in contact with the epitaxial layer 3 or the p type well 12 cannot be provided in the IG FET shown in FIG. 2, it is impossible to give a specified back gate bias to the p type epitaxial layer or to the p type well 12 in accordance with the circuit configuration and the requirements of operation. Thus, strongly hoped for is the advent of a novel complementary integrated circuit having of plural IG FETs and including a buried insulating film in which the above mentioned disadvantages are eliminated.